1. Field of the Invention
This invention relates to data processing systems and more particularly to a general purpose computer system having alternate paths for addressing data in memory wherein one path is for normal addressing and the other is for automatic use in the event of memory failure.
2. Description of the Prior Art
As data processing systems have become more complex the size and number of processors, main memories and peripheral units has grown. It has therefore become imperative that communication links between processor, peripherals and main memory be maintained. Because of the high cost of providing redundant processors for controlling communications between peripheral units on input/output exchange was utilized for coupling a plurality of peripheral units to central processing unit. When this input/output exchange failed, access to the central processing unit by all peripheral units coupled to that input/output exchange was blocked. One answer to this dilemma was to provide redundant paths by providing at least one additional output exchange, to which all the peripheral controllers and peripheral units are connected. (See U.S. Pat. No. 3,792,448 issued Feb. 12, 1974 to Bennett et al and entitled "Fail Soft Peripheral Exchange".)
This did not solve the problem, however, where a peripheral itself such as a main memory failed. If, for example, there were a failure in one module or portion of main memory which stored the base addresses of routines or programs stored in the good portion of the main memory or module, these routines or programs in the good portion of the module would not automatically be accessible to the processor.
What is needed therefore is a mechanism for automatically providing an alternate addressing path to the good portion of memory.